A Time-Domain Comparator Based Skipping-Window SAR ADC

This paper presents an energy efficient successive-approximation register (SAR) analog-to-digital converter (ADC) for low-power applications. To improve the overall energy-efficiency, a skipping-window technique is used to bypass corresponding conversion steps when input falls in window indicated by time-domain comparator, which can provide not only polarity of input, but also amount information input. The based on edge pursing principle, consists delay cells, two NAND gates, D-flip-flop register-based phase detectors and counter. digital characteristic comparator makes design more flexible, achieve noise power optimization automatically simply adjusting cell number. An digital-to-analog (DAC) control scheme suitable skipping developed reduce switching during SAR conversion. Together with technique, linearity consumption ADC are improved. impact different sizes comparison cycles, DAC efficiency analyzed. Simulation results show that proposed energy-efficiency ADC, as well linearity, optimized size will vary energy.